ASM5P2305A

October 2006

ASM5P2309A

rev 2.2

3.3V Zero Delay Buffer

2 of 19

Notice: The information in this document is subject to change without notice.

Select Input Decoding for ASM5P2309A

S2

S1

Clock A1 - A4

Clock B1 - B4

CLKOUT

1

Output Source

PLL

Shut-Down

0

0

Three-state

Three-state

Driven

PLL

N

0

1

Driven

Three-state

Driven

PLL

N

1

0

Driven

Driven

Driven

Reference

Y

1

1

Driven

Driven

Driven

PLL

N

Notes:

1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the

output.

Zero Delay and Skew Control

All outputs should be uniformly loaded to achieve Zero

Delay between input and output. Since the CLKOUT pin is

the internal feedback to the PLL, its relative loading can

adjust the input-output delay.

For applications requiring zero input-output delay, all

outputs, including CLKOUT, must be equally loaded. Even

if CLKOUT is not used, it must have a capacitive load equal

to that on other outputs, for obtaining zero-input-output

delay.