LE25FW808

No.A0839-5/27

Device Operation

The LE25FW808 features electrical on-chip erase functions using a single 3.0V power supply, that have been added to

the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are facilitated by

incorporating the command registers inside the chip. The read, erase, program and other required functions of the

device are executed through the command registers. The command addresses and data input in accordance with "Table

2 Command Settings" are latched inside the device in order to execute the required operations. "Figure 3 Serial Input

Timing" shows the timing waveforms of the serial data input. First, at the falling CS edge the device is selected, and

serial input is enabled for the commands, addresses, etc. These inputs are introduced internally in sequence starting with

bit 7 in synchronization with the rising SCK edge. At this time, output pin SO is in the high-impedance state. The

output pin is placed in the low-impedance state when the data is output in sequence starting with bit 7 synchronized to

the falling clock edge during read, status register read and silicon ID. Refer to "Figure 4 Serial Output Timing" for the

serial output timing.

The LE25FW808 supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is

automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of

SCK is high.

Figure 3 Serial Input Timing

Figure 4 Serial Output Timing

High Impedance

tDH

tCPH

tDS

tCSH

tCSS

CS

DATA VALID

SO

SI

SCK

High Impedance

tCLH

tCLS

tCLHI

tCLLO

tHO

tCHZ

tCLZ

SI

tV

CS

SO

SCK

DATA VALID