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TPS65192 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS65192 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 25 page ![]() TYPICAL CHARACTERISTICS TABLE OF GRAPHS TPS65192 www.ti.com ....................................................................................................................................................................................................... SLVS962 – JULY 2009 PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. OUT8 20 O Level shifter channel 8 output. Leave this pin floating, if not used. OUT9 21 O Level shifter channel 9 output. Leave this pin floating, if not used. DISCHARGE 22 O Panel discharge output. Leave this pin floating, if not used. GND 23 P Ground. RE 24 O Gate voltage shaping discharge resistor connection. Leave this pin floating, if not used. FLK3 25 I Gate voltage shaping flicker clock input for channels 3 and 6. Connect this pin to GND if not used. FLK2 26 I Gate voltage shaping flicker clock input for channels 2 and 5. Connect this pin to GND if not used. FLK1 27 I Gate voltage shaping flicker clock input for channels 1 and 4. Connect this pin to GND if not used. VSENSE 28 I Panel discharge voltage sense. Connect this pin to GND, if not used. Exposed Pad P Connect to VGL Thermal Die FIGURE Output Rise and Fall Time Channels 1 to 7, CL = 4.7 nF, rising edge Figure 1 Channels 1 to 7, CL = 4.7 nF, falling edge Figure 2 Channels 8 to 9, CL = 4.7 nF, rising edge Figure 3 Channels 8 to 9, CL = 4.7 nF, falling edge Figure 4 Channels 1 to 7, CL = 8 pF, rising edge Figure 5 Channels 1 to 7, CL = 8 pF, falling edge Figure 6 Channels 8 to 9, CL = 8 pF, rising edge Figure 7 Channels 8 to 9, CL = 8 pF, falling edge Figure 8 Propagation Delay IN to OUT, channels 1 to 7, CL = 150 pF, rising edge Figure 9 IN to OUT, channels 1 to 7, CL = 150 pF, falling edge Figure 10 IN to OUT, channels 8 to 9, CL = 150 pF, rising edge Figure 11 IN to OUT, channels 8 to 9, CL = 150 pF, falling edge Figure 12 FLK to OUT, channels 1 to 6, CL = 150 pF, RE = 1 kΩ Figure 13 Output Current Channels 1 to 7, CL = 10 nF Figure 14 Channels 8 to 9, CL = 10 nF Figure 15 Panel Discharge Power-on sequencing Figure 16 Power-off-sequencing Figure 17 Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS65192 |
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