LT3070EUFD datasheet(13/24 Pages) LINER

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LT3070

3070p

APPLICATIONS INFORMATION

positive voltage margining. The voltage range between

these two logic thresholds deﬁnes the logic Hi-Z state

and disables the margining function.

The MARGTOL pin selects the absolute value of margining

(1%, 3% or 5%) if enabled by the MARGSEL input. The

logic “low” threshold is less than 220mV referenced to

GND and enables either ±1% change in VOUT depending on

the state of the MARGSEL pin. The logic “high” threshold

is greater than VBIAS – 500mV and enables either ±5%

change in VOUT depending on the state of the MARGSEL

pin. The voltage range between these two logic thresholds

deﬁnes the logic Hi-Z state and enables either ±3% change

in VOUT depending on the state of the MARGSEL pin.

Table 2: Programming Margining

MARGSEL

MARGTOL

% of VOUT(NOM)

–1

–3

–5

Z00

ZZ0

Z10

101

1Z3

115

Enable Function—Turning On and Off

The ﬁrst rising edge of the EN enable pin starts the LT3070

reference and all support functions while enabling the

output. After start-up, pulling the EN pin low places the

regulator into nap mode. In nap mode, the reference circuit

remains active, but the output is disabled and quiescent

current decreases.

Drive the EN pin with either a digital logic port or an open-

collector NPN or open-drain NMOS terminated with a

pull-up resistor to VBIAS. The pull-up resistor must be no

larger than 35k to meet the VIH condition of the EN pin. If

unused, connect the EN pin to VBIAS.

Input Undervoltage Lockout on BIAS Pin

An internal undervoltage lockout (UVLO) comparator

monitors the BIAS rail. If VBIAS drops below the UVLO

threshold, all functions shut down, the pass transistor is

gated off and output current falls to zero. The typical BIAS

pin UVLO threshold is 1.55V on the rising edge of VBIAS.

The UVLO circuit incorporates about 250mV of hysteresis

on the falling edge of VBIAS.

High Efﬁciency Linear Regulator—Input-to-Output

Voltage Control

The VIOC (voltage input to output control) pin is a function

to control a switching regulator and facilitate a design solu-

tion that maximizes system efﬁciency at high load currents

and still provides low dropout voltage performance.

The VIOC pin is the output of an integrated transconduc-

tance ampliﬁer that sources and sinks 250μA of current.

It typically regulates the output of most LTC

® switching

regulators or LTM

® power modules, by sinking current

from the ITH compensation node. The VIOC function

controls a buck regulator powering the LT3070’s input by

maintaining the LT3070’s input voltage to VOUT + 300mV.

This 300mV VIN-VOUT differential voltage is chosen to

provide fast transient response and good high frequency

PSRR while minimizing power dissipation and maximizing

efﬁciency. For example, 1.5V to 1.2V conversion and 1.3V

to 1V conversion yield 1.5W maximum power dissipation

at 5A full output current.

Figure 2 depicts that the switcher’s feedback resistor net-

work sets the maximum switching regulator output voltage

if the linear regulator is disabled. However, once the LT3070

is enabled, the VIOC feedback loop decreases the switching

regulator output voltage back to VOUT + 300mV.

Using the VIOC function creates a feedback loop between

the LT3070 and the switching regulator. As such, the

feedback loop must be frequency compensated for stabil-

ity. Fortunately, the connection of VIOC to many LTC ITH

pins represents a high impedance characteristic which is

the optimum circuit node to frequency compensate the

feedback loop. Figure 2 illustrates the typical frequency

compensation network used at the VIOC node to GND.

The VIOC ampliﬁer characteristics are:

gm = 3.2mS, IOUT = ±250μA, BW = 10MHz.

If the VIOC is not used, terminate the VIOC pin to GND with

a small capacitor (1000pF) to prevent oscillations.

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