CYDM064B16, CYDM128B16, CYDM256B16
Document #: 001-00217 Rev. *F
Page 13 of 24
Write Cycle
tWC
Write Cycle Time
55
ns
tSCE
[24]
CE LOW to Write End
45
ns
tAW
Address Valid to Write End
45
ns
tHA
Address Hold From Write End
0
ns
tSA
[24]
Address Setup to Write Start
0
ns
tPWE
Write Pulse Width
40
ns
tSD
Data Setup to Write End
30
ns
tHD
Data Hold From Write End
0
ns
tHZWE
[26, 27]
R/W LOW to High Z
25
ns
tLZWE
[26, 27]
R/W HIGH to Low Z
0
ns
tWDD
[28]
Write Pulse to Data Delay
80
ns
tDDD
[28]
Write Data Valid to Read Data Valid
80
ns
Busy Timing[29]
tBLA
BUSY LOW from Address Match
45
ns
tBHA
BUSY HIGH from Address Mismatch
45
ns
tBLC
BUSY LOW from CE LOW
45
ns
tBHC
BUSY HIGH from CE HIGH
45
ns
tPS
[30]
Port Setup for Priority
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
35
ns
tBDD
[31]
BUSY HIGH to Data Valid
40
ns
Interrupt Timing[29]
tINS
INT Set Time
45
ns
tINR
INT Reset Time
45
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)15
ns
tSWRD
SEM Flag Write to Read Time
10
ns
tSPS
SEM Flag Contention Window
10
ns
tSAA
SEM Address Access Time
55
ns
Switching Characteristics for VCC = 1.8V (continued)
Over the Operating Range[23]
Parameter
Description
CYDM256B16, CYDM128B16, CYDM064B16
Unit
-55
Min
Max
Notes
28. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
29. Test conditions used are Load 2.
30. Add 2ns to this parameter if VCC and VDDIOR are <1.8V, and VDDIOL is >2.5V at temperature <0°C.
31. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
