21 / 24 page
CYDM064B16, CYDM128B16, CYDM256B16
Document #: 001-00217 Rev. *F
Page 21 of 24
Figure 11. Busy Timing Diagram No.1 (CE Arbitration)
Figure 12. Busy Timing Diagram No.2 (Address Arbitration) [50]
Note
50. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY iS asserted.
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC
tBHC
ADDRESS MATCH
tPS
tBLC
tBHC
CER Valid First
ADDRESSL,R
BUSYR
CEL
CER
BUSYL
CER
CEL
ADDRESSL,R
CEL Valid First
[50]
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA
tBHA
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
BUSYL
tRC or tWC
tBLA
tBHA
ADDRESSR
Right Address Valid First
Left Address Valid First
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