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SPT7938

In cases in which wider variations in offset and gain can be

and sense lines to AGND with a 0.01

µF capacitor (chip cap

preferred) to minimize high-frequency noise injection. If this

simplified configuration is used, the following considerations

should be taken into account:

The reference ladder circuit shown in figure 4 is a simplified

representation of the actual reference ladder with force and

sense taps shown. Due to the actual internal structure of the

equal:

Figure 4 shows an example of expected voltage drops for a

ANALOG INPUT

spect to the voltage reference. (See the Voltage Reference

section.)

The drive requirements for the analog inputs are very mini-

mal when compared to most other converters due to the

SPT7938’s extremely low input capacitance of only 20 pF

and very high input resistance in excess of 25 k

Ω.

The analog input should be protected through a series resis-

tor and diode clamping circuit as shown in figure 5. To pre-

vent possible latch-up condition, the power supplies must

be powered up before the input is applied.

Figure 4 – Simplified Reference Ladder Drive Circuit

Without Force/Sense Circuit

R/2

R

R

R

R

R

R

R/2

R=30

Ω (typ)

All capacitors are 0.01

µF

0.0 V

(0.050 V)

(+3.98 V)

21 mV

50 mV

+4.0 V

External

Reference

CALIBRATION

The SPT7938 uses a user-transparent, auto-calibration

scheme to ensure 12-bit accuracy over time and tempera-

ture. Gain and offset errors are continually adjusted to 12-bit

accuracy during device operation.

Upon powerup, the SPT7938 begins its calibration algo-

rithm. In order to achieve the calibration accuracy required,

the offset and gain adjustment step size is a fraction of a 12-

bit LSB. Since the calibration algorithm is an oversampling

process, a minimum of 10,000 clock cycles are required.

This results in a minimum calibration time upon power-up of

250

µsec (for a 40 MHz clock). Once calibrated, the

SPT7938 remains calibrated over time and temperature.

Since the calibration cycles are initiated on the rising edge

of the clock, the clock must be continuously applied for the

SPT7938 to remain in calibration.

Figure 5 – Recommended Input Protection Circuit

47

Ω

D1

D2

ADC

Buffer

+V

–V

D1 = D2 = Hewlett Packard HP5712 or equivalent