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SPT7938

Figure 6 – On-Chip Protection Circuit

Analog

Pad

120

Ω

120

Ω

INPUT PROTECTION

All I/O pads are protected with an on-chip protection circuit

shown in figure 6. This circuit provides ESD robustness to

3.5 kV and prevents latch-up under severe discharge condi-

tions without degrading analog transition times.

CLOCK INPUT

The SPT7938 is driven from a single-ended TTL-input

clock. The duty cycle of the clock should be kept as close to

50% (

±5%) as possible.

DIGITAL OUTPUTS

The digital outputs (D0–D12) are driven by a separate sup-

possible to drive the SPT7938’s TTL/CMOS-compatible

outputs with the user’s logic system supply. The format of

the output data (D0–D11) is straight binary. (See table III.)

The outputs are latched on the rising edge of CLK. These

high.

Table III – Output Data Information

ANALOG INPUT

OVERRANGE

OUTPUT CODE

D12

D11–D0

+F.S. + 1/2 LSB

1

11 1111

1111

+F.S. –1/2 LSB

0

11 1111

111Ø

+1/2 F.S.

0

ØØ ØØØØ ØØØØ

+1/2 LSB

0

00 0000

000Ø

0.0 V

0

00 0000

0000

(Ø indicates the flickering bit between logic 0 and 1).

OVERRANGE OUTPUT

The Overrange Output (D12) is an indication that the analog

input signal has exceeded the positive full-scale input volt-

age by 1 LSB. When this condition occurs, D12 will switch to

logic 1. All other data outputs (D0 to D11) will remain at

logic 1 as long as D12 remains at logic 1. This feature

makes it possible to include the SPT7938 in higher resolu-

tion systems.

EVALUATION BOARD

The EB7938 evaluation board is available to aid designers

in demonstrating the full performance of the SPT7938. This

board includes a reference circuit, clock driver circuit, output

data latches and an on-board reconstruction of the digital

data. An application note (AN7938) describing the operation

of this board, as well as information on the testing of the

SPT7938, is also available. Contact the factory for price and

availability.