SPT8100 datasheet(8/10 Pages) CADEKA

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SPT8100

Figure 5 – Timing Diagram 2

CLK

Digital

Outputs

tD1

tD2

tD3

Table II – Timing Parameters

Parameter

Symbol

Min

Typ Max

Units

CLK high to Data Valid

tD1

401

OE inactive to HiZ

tD2

OE active to Data Valid

tD3

Conditions: load capacitance = 20 pF, VOH = 3.3 V

FFT Plot

Typical Differential Linearity Error (DLE)

Test Conditions:

ƒIN = 2 MHz

ƒCLK = 4.4 MHz

PGA Gain = 18 dB

REXT = 1.08 kΩ

ADC Input (Post PGA) = –5.4 dBFS

TA = +25 °C

Test Conditions:

ƒIN = 75 kHz

ƒCLK = 4.4 MHz

PGA Gain = 0 dB

Near Full-Scale Input

Two-Tone Intermodulation FFT

Spurious-Free Dynamic Range

100

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

5 VP-P

0.9 MHz, low

0.9 MHz, high

0.9 MHz, med

2 MHz, high

2 MHz, med

2 MHz, low

3 MHz, high

3 MHz, med

3 MHz, low

Composite Level at ADC Input (dBFS)

Test Conditions:

ƒ1 = 890 kHz

ƒ2 = 900 kHz

ƒCLK = 4.4 MHz

PGA Gain = 6 dB

REXT = 1.43 kΩ

ADC Input (Post PGA) = –8.0 dBFS

TA = +25 °C

Test Conditions:

10 MSPS, 5 V, 25 °C

Low: REXT=1.43 kΩ @96 mA

Med: REXT=1.24 kΩ @109 mA

High: REXT=1 kΩ @129 mA

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