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SPT8100 Datasheet(PDF) 10 Page - Cadeka Microcircuits LLC. |
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SPT8100 Datasheet(HTML) 10 Page - Cadeka Microcircuits LLC. |
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10 / 10 page ![]() 10 1/9/02 SPT8100 PIN ASSIGNMENTS PIN FUNCTIONS Pin Name Description AGND Analog ground DGND Digital ground DVDD Digital +5.0 V supply OGND Ground for digital I/O OVDD Digital outputs supply (+3.3/5 V) CLK Master reference clock OE Output enable (active high) D0–D15 Data output bits; D0 is LSB; D15 is MSB OVR Overrange indicator bit (active high) N/C No connect GS[2:0] 3-bit PGA gain setting control inputs AVDD Analog +5.0 V supply RS Resets internal state of chip (active low) RDY Initialization in progress indicator; RDY goes low during reset initialization. Chip is ready for normal operation when RDY is high. BIASC External bias capacitor connection BIASR External bias resistor connection VRT, VRB ADC reference voltage outputs VCM Common mode reference voltage output VIN+, VIN– Analog inputs to the PGA 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 AGND DGND DVDD DVDD OGND OVDD CLK OE D0 (LSB) D1 D2 RDY N/C N/C AGND AVDD GS2 N/C OVR D15 (MSB) D14 RS ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE SPT8100SIT –40 to +85 °C 44L LQFP |
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