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TMC22051AKHC Datasheet(PDF) 9 Page - Cadeka Microcircuits LLC. |
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TMC22051AKHC Datasheet(HTML) 9 Page - Cadeka Microcircuits LLC. |
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9 / 84 page  PRODUCT SPECIFICATION TMC22x5yA REV. 1.0.0 2/4/03 9 0D 7-6 CEST Chroma error signal transform 0D 5 CESG Chroma error signal gain 0D 4 YESG Luma error signal gain 0D 3 CESTBY Chroma error signal bypass 0D 2 XFEN XLUT filter enable 0D 1 FAST Adaption speed select 0D 0 YWBY Luma weighting bypass 0E 7-6 XIP XLUT input select 0E 5-4 XSF XLUT special function 0E 3-2 YMUX Y output select 0E 1-0 CMUX C output select 0F 7 reserved, set to zero 0F 6-5 CAT Adaption Threshold 0F 4 DCES D1 CBCR error signal 0F 3-2 IPCF Comb filter input select 0F 1 YCCOMP YC or Composite input select 0F 0 SYNC Sync processor select Sync Pulse Generator 10 7-0 STS7-0 Sync to sync 8 lsbs 11 7-0 STB Sync to burst 12 7-0 BTV Burst to video 13 7-0 AV7-0 Active video line 8 lsbs 14 7-6 reserved, set to zero 14 5-4 AV9-8 Active video line 2 msbs 14 3 reserved, set to zero 14 2-0 STS10-8 Sync to sync 3 msbs 15 7 reserved, set to zero 15 6-2 VINDO Number of lines in vertical window 15 1 VDIV Action inside VINDO 15 0 VDOV Action outside VINDO 16 7-6 reserved, set to zero 16 5-4 NFDLY new field detect delay 16 3-2 SPGIP SPG input select 16 1-0 MSIP Mixed sync separator input select Buffered register set 0 Active when BUFFER pin set LOW 17 7-0 SG07-0 Msync gain, 8 lsbs 18 7-0 YG07-0 Y gain, 8 lsbs 19 7-0 UG07-0 U gain, 8 lsbs Reg Bit Name Function 1A 7-0 VG07-0 V gain, 8 lsbs 1B 7-6 YG09-8 Y gain, 2 msbs 1B 5-3 UG010-8 U gain, 3 msbs 1B 2 reserved, set to zero 1B 1-0 VG09-8 V gain, 2 msbs 1C 7-0 YOFF07-0 Y offset, 8 lsbs 1D 7-3 reserved, set to zero 1D 2 YOFF08 Y offset, msb 1D 1-0 SG07-0 Msync gain, 2 msbs 1E 7-1 SYSPH06-0 7 lsbs of phase 1E 0 VAXISO V axis flip 1F 7-0 SYSPH014-7 8 msbs of phase Normalized Subcarrier Frequency 20 7-4 FSC3-0 Bottom 4 bits of fSC 20 3-0 reserved, set to zero 21 7-0 FSC11-4 Lower 8 bits of fSC 22 7-0 FSC19-12 Middle 8 bits of fSC 23 7-0 FSC27-20 Top 8 bits of fSC Clamp Control 24 7 DRFSEL Clamp pulse enable 24 6 PFLTBY Phase filter enable 24 5-4 CLPSEL1-0 Int. clamp selection 24 3 VCLPEN Clamp bypass 24 2-0 BAND2-0 Clamp offset 25 7-0 CPDLY7-0 Clamp pulse delay Output Format Control 26 7-6 reserved, set to zero 26 5 LDVIO LDV clock select 26 4 OPCKS Output clock select 26 3 DPCEN DPC enable 26 2-0 DPC Decoder product code Buffered register set 1 Active when BUFFER pin set HIGH 27 7-0 SG17-0 Msync gain, 8 lsbs 28 7-0 YG17-0 Y gain, 8 lsbs 29 7-0 UG17-0 U gain, 8 lsbs 2A 7-0 VG17-0 V gain, 8 lsbs 2B 7-6 YG19-8 Y gain, 2 msbs 2B 5-3 UG110-8 U gain, 3 msbs 2B 2 reserved, set to zero 2B 1-0 VG19-8 V gain, 2 msbs 2C 7-0 YOFF17-0 Y offset, 8 lsbs 2D 7-3 reserved, set to zero Reg Bit Name Function |
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