TMC1175A datasheet(3/18 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC1175A

REV. 1.3.3 2/28/02

Table 1. Output Coding

Note:

1. LSB = (RT – RB) / 255

Digital Inputs and Outputs

Sampling of the applied input signal takes place on the fall-

ing edge of the CONV signal (Figure 2). The output word is

delayed by 2 1/2 CONV cycles. It is then available after the

rising edge of CONV. The previous data on the output

Input Voltage

Output

RT + 1 LSB

RT – 1 LSB

• • •

RB + 128 LSB

RB + 127 LSB

• • •

RB + 1 LSB

RB – 1 LSB

remain valid for tHO (Output Hold Time), satisfying any

hold time requirement of the receiving circuit. The new data

become valid tDO (Output Delay Time) after this rising edge

of CONV.

The outputs of the TMC1175A are CMOS- and TTL-com-

patible, and are capable of driving four low-power Schottky

TTL (54/74LS) loads. An Output Enable control, OE, places

the outputs in a high-impedance state when HIGH. The out-

puts are enabled when OE is LOW.

Power and Ground

To minimize noise injection into the analog section, VDDA

may be connected to a separate regulated +5 volt supply.

VDDD may be connected to a digital supply. Power up

sequence is immaterial. Latch-up will not occur.

AGND and DGND pins should be connected to a common

ground plane. For optimum performance treat analog and

digital PWB traces as transmission lines. Route analog

connections cleanly to the TMC1175A. Segregate digital

connections and if necessary terminate clocks to eliminate

ringing. Prevent digital returm currents from ﬂowing across

analog input sections of the TMC1175A.

Figure 2. Conversion Timing

CONV

D7-0

ORP

ORN

VIN

24455A

Data N–3

Data N–2

Data N–1

Data N

tSTO

tPWL

tHO

tDIS

tENA

tDO

tPWH

1/fS

Hi-Z

Sample N

Sample N+1

Sample N+2

Sample N+3

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