CONNECTING THE ADC150

POWER SUPPLIES

The power supply lines are connected to pins 4-7.

Pin 4 is -15V, pin 5 is +15V, pin 6 is +5V and pin 7

is GND.

OUTPUT DATA LINES

The output data is available in byte form on pins

13-20. Pin 20 is the Most Significant Bit and pin 13

the Least Significant Bit. The data lines go to a high

impedance state when the Output Enable line is at a

logic one level.

OUTPUT ENABLE (PIN 21)

Data is placed on the Output Data Lines by a logic

zero on this line.

See figure 2 for data output

format.

CONVERT (Pin22)

This line is used to initiate a conversion cycle and

to retrieve the output data. The status lines indicate

which function will be executed.

The first pulse

(transition from logic one to logic zero) starts the

conversion cycle. Two subsequent pulses are used

to place the lower two bytes on the Output Data

Lines. See figure 4 for timing diagram.

STATUS LINES (Pins 23, 24)

These lines indicate the present state of the ADC.

When the Convert line receives the first pulse in a

conversion cycle the Status Lines go to logic zero,

indicating that a conversion cycle is in progress.

When

the

conversion

is

complete

the

microprocessor places the MSB of the output data

in the output buffer and then raises S

one, indicating that the MSB at the output data is

available in the output buffer.

When the Convert

Line is pulsed again the middle byte of the output

data is placed in that output buffer and S

to logic one and S

The third pulse

places the LSB of the output data in the buffer and

both status lines go to the logic one. The converter

is now ready for the next conversion cycle.

See

figure 5 for timing diagrams.

The table below shows a summary of the status

code.

Conversion in process.

Conversion complete. MSB in output.

Middle byte in output register.

LSB in output. Ready for next conversion.

0

0

0

1

1

0

1

1

S

1

S

0

MODE CONTROL (Pin 25)

This line is used to program the ADC150.

The

mode control byte (8 bit) is placed on the data bus.

Pin 25 is then set to logic high, pin 21 is pulsed low

to accept the control byte. Pin 22 is then pulsed low

and held low until the status lines return high

(~2ms). Pin 21 is then pulsed high and pin 25 is

then returned to logic low. The ADC150 has now

been reset to the new parameters. See figure 6 for

timing diagrams.

The mode control byte is defined as follows:

Bits 7 and 6 - unused

Bits 5 and 4 - 00 Pin 39 signal input, autozero*

01 Pin 38 signal input

Bit 3

- 0 60 Hz.*

1 50 Hz.

Bits 2,1, 0

- 001 18 Bit

010 20 Bit

011 22 Bit*

100 24 Bit

* Factory default settings

AUTO-ZERO / RESET (Pin 29)

A logic zero on this input will autozero the ADC150

by internally connecting the analog high to analog

low. Since the µP is reset, the ADC150 reverts to

the factory default settings in the EPROM (ie.

22bits, 60Hz, pin 39 analog high).

To select a

mode different than the default settings, the mode

control must be set after auto zero. See figure 3 for

timing diagrams.

INTEGRATION CAPACITOR (Pin 34, 35)

A 0.68 µF polystyrene or Mylar must be connected

to these pins. Lead length should be as short as

possible and not exceed 2".

ANALOG INPUTS (Pin 39, 40)

Both analog inputs are buffered by op-amps and

have a common mode rejection of approximately

80dB minimum. To maintain the full accuracy at the

ADC it is recommended to keep the input to analog

low to less than 0.1VDC.

ADC150DS REV. F MAR 00