iiiiiPEM

PEM

PEM

PEM

PEM

2.4G

2.4G

2.4G

2.4G

2.4Gb SDRAM-DDR

b SDRAM-DDR

b SDRAM-DDR

b SDRAM-DDR

b SDRAM-DDR

AS4DDR32M72PBG

AS4DDR32M72PBG

Rev. 1.2 06/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

Austin Semiconductor, Inc.

32Mx72 DDR SDRAM

iNTEGRATED Plastic Encapsulated Microcircuit

FEATURES

DDR SDRAM Data Rate = 200, 250, 266, 333Mbps

Package:

2.5V ±0.2V core power supply

2.5V I/O (SSTL_2 compatible)

Differential clock inputs (CLK and CLK#)

Commands entered on each positive CLK edge

Internal pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

Programmable Burst length: 2,4 or 8

Bidirectional data strobe (DQS) transmitted/received

with data, i.e., source-synchronous data capture

(one per byte)

DQS edge-aligned with data for READs; center-aligned

with data for WRITEs

DLL to align DQ and DQS transitions with CLK

Four internal banks for concurrent operation

Two data mask (DM) pins for masking write data

Programmable IOL/IOH option

Auto precharge option

Auto Refresh and Self Refresh Modes

Industrial, Enhanced and Military Temperature

Ranges

Organized as 32M x 72/80

Weight: AS4DDR32M72PBG </= 3.10 grams typical

* This product and or it’s specifications is subject to change without notice.

BENEFITS

40% SPACE SAVINGS

Reduced part count

Reduced I/O count

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

Laminate interposer for optimum TCE match

O

P

T

I

O

N

S

Area

I/O

Count

11.9

Monolithic Solution

11.9

11.9

11.9

5 x 265mm2 = 1328mm2 Plus

5 x 66 pins = 320 pins

11.9

32

25

Integrated MCP Solution

S

A

V

I

N

G

S

22.3

800mm2

40+%

219 Balls

34 %

Configuration Addressing

Parameter

32 Meg x 72

Configuration

8 Meg x 16 x 4 Banks

Refresh Count

8K

Row Address

8K (A0 A12)

Bank Address

4 (BA0 BA1)

Column Address

1K (A0 A9)