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AS4SD4M16DG-10/IT Datasheet(PDF) 13 Page - Austin Semiconductor |
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AS4SD4M16DG-10/IT Datasheet(HTML) 13 Page - Austin Semiconductor |
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13 / 50 page  SDRAM SDRAM SDRAM SDRAM SDRAM AS4SD4M16 AS4SD4M16 Rev. 2.1 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 Austin Semiconductor, Inc. READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command, and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the comple- tion of the burst. For the generic READ commands used in the following illustrations, AUTO PRECHARGE is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of alonger burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. Figure 5 READ COMMAND 12345 12345 12345 CLK CKE HIGH CS\ 12345678 12345678 12345678901 12345678901 1 1 1 1 123456 123456 1234567890 1234567890 1 1 1 1 RAS\ 12345678 12345678 12345678 12345678901 12345678901 12345678901 1 1 1 1 1 1 123456 123456 123456 1234567890 1234567890 1234567890 1 1 1 1 1 1 12345678 12345678 12345678 12345678 12345678 12345678 1 1 1 1 1 1 1234567890123 1234567890123 1234567890123 1 1 1 1 1 1 CAS\ 12345678 12345678 12345678 12345678 12345678 12345678 1 1 1 1 1 1 123456 123456 123456 1234567890123 1234567890123 1234567890123 1 1 1 1 1 1 WE\ 123 123 123 12345678901234 12345678901234 12345678901234 1 1 1 12 12 12 1234 1234 1234 12345678901 12345678901 12345678901 1 1 1 12 12 12 123 123 123 12345678901234 12345678901234 12345678901234 1 1 12 12 1234 1234 1234 12345678901 12345678901 12345678901 1 1 12 12 A0-A7: x16 BA0, 1 COLUMN ADDRESS BANK ADDRESS 123 123 123 123 12345678 12345678 1 1 1 1 123 123 12345678901234 12345678901234 1 1 12 12 1234 1234 12345678901 12345678901 1 1 12 12 123 123 123 12345678901234 12345678901234 12345678901234 1 1 1 12 12 12 1234 1234 1234 12345678901 12345678901 12345678901 1 1 1 12 12 12 ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE A8, A9, A11: x16 A10 Figure 6 CAS LATENCY 123 123 123 123 1234 1234 1234 1234 DON’T CARE UNDEFINED CLK COMMAND DQ tLZ t OH tAC CAS Latency = 3 123 123 123 12 12 12 123 123 123 123 123 123 READ NOP 1234567 1234567 1234567 1234567 DOUT 1234 1234 1234 1234 T0 T1 T2 T3 123 123 123 NOP T4 123 123 123 NOP CLK COMMAND DQ tLZ tOH tAC CAS Latency = 2 123 123 123 123 12 12 12 12 123 123 123 123 123 123 123 123 READ NOP 1234567 1234567 1234567 1234567 DOUT 1234 1234 1234 1234 T0 T1 T2 T3 123 123 123 123 NOP |
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