AD7780

Rev. A | Page 11 of 16

THEORY OF OPERATION

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INPUT SIGNAL FREQUENCY (Hz)

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The AD7780 is a low power ADC that incorporates a precision

24-bit, Σ-Δ modulator; a PGA; and an on-chip digital filter

intended for measuring wide dynamic range, low frequency

signals. The part provides a complete front-end solution for

bridge sensor applications such as weigh scales and pressure

sensors.

The device has an internal clock and one buffered differential

input. It offers a choice of two update rates (10 Hz or 16.7 Hz)

and two gain settings (1 or 128). These functions are controlled

using dedicated pins, which makes the interface easy to configure.

A 2-wire interface simplifies data retrieval from the AD7780.

FILTER, DATA RATE, AND SETTLING TIME

The AD7780 has two filter options. When the FILTER pin is low,

the 16.7 Hz filter is selected; when the FILTER pin is high, the

10 Hz filter is selected. When the polarity of FILTER is changed,

the AD7780 modulator and filter are reset immediately. DOUT/

RDY is set high, and the ADC then begins conversions using

the selected filter response. The first conversion requires the

complete settling time of the filter. Subsequent conversions occur

at the selected update rate. The settling time of the 10 Hz filter is

300 ms (three conversion cycles), and the settling time of the

16.7 Hz filter is 120 ms (two conversion cycles).

Figure 20. Filter Profile with Update Rate = 16.7 Hz (FILTER = 0)

01

100

80

60

40

20

INPUT SIGNAL FREQUENCY (Hz)

–1000

0

–20

–40

–60

–80

–100

20

When a step change occurs on the analog input, the AD7780

requires several conversion cycles to generate a valid conversion.

If the step change occurs synchronous to the conversion period, the

settling time of the AD7780 must be allowed to generate a valid

conversion. If the step change occurs asynchronous to the end

of a conversion, an extra conversion must be allowed to generate

a valid conversion. The data register is updated with all the con-

versions, but, for an accurate result, the user must allow for the

required time.

Figure 21. Filter Profile with Update Rate = 10 Hz (FILTER = 1)

Figure 20 and Figure 21 show the filter response for each filter.

The 10 Hz filter provides greater than −45 dB of rejection in the

stop band. The only external filtering required on the analog inputs

is a simple R-C filter to provide rejection at multiples of the master

clock. A 1 kΩ resistor in series with each analog input, a 0.01 μF

capacitor from each input to GND, and a 0.1 μF capacitor from

AIN(+) to AIN(−) are recommended.

When the filter is changed, DOUT/RDY goes high and remains

high until the appropriate settling time for that filter elapses

(see

). Therefore, the user should complete any read

operations before changing the filter. Otherwise, 1s are read

back from the AD7780 because the DOUT/

Figure 5

RDY pin is set high

following the filter change.