ADCLK846

Rev. A | Page 14 of 16

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the ADCLK846 do not supply enough

current to provide a full voltage swing with a low impedance

resistive, far-end termination, as shown in Figure 27. Match the

far-end termination network to the PCB trace impedance and

provide the desired switching point. The reduced signal swing

may still meet receiver input requirements in some applications.

This can be useful when driving long trace lengths on less

critical nets.

CMOS

CMOS

10Ω

50Ω

100Ω

100Ω

Figure 27. CMOS Output with Far-End Termination

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The ADCLK846 offers LVDS outputs

that are better suited for driving long traces where the inherent

noise immunity of differential signaling provides superior

performance for clocking converters.

INPUT TERMINATION OPTIONS

For single-ended operation, always bypass unused input to

GND as shown in Figure 31.

to negate the 30 mV input offset with external resistor values.

For example, use 1.8 V CMOS with long traces to provide far-

end termination.

100Ω

CLK

CLK

100Ω

CLK

CLK

Figure 28. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configurations

(see Table 8)

CLK

CLK

CLK

CLK

Figure 29. Typical AC-Coupled or DC-Coupled CML Configurations

(see Table 8 for CML Coupling Limitations)

CLK

CLK

50Ω

50Ω

CLK

CLK

50Ω

50Ω

Figure 30. Typical AC-Coupled or DC-Coupled LVPECL Configurations

(see Table 8 for LVPECL DC Coupling Limitations)

CLK

CLK

CLK

CLK

CLK

CLK

Figure 31. Typical 1.8 V CMOS Configurations for Short Trace Lengths

(see Table 8 for CMOS compatibility)

CLK

CLK