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25LC040AX-I/ST Datasheet(PDF) 12 Page - Microchip Technology |
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25LC040AX-I/ST Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 30 page  25AA040A/25LC040A DS21827F-page 12 © 2009 Microchip Technology Inc. 2.7 Data Protection The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset •CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued 2.8 Power-On State The 25XX040A powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low-level transition on CS is required to enter active state TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX WP (pin 3) WEL (SR bit 1) Protected Blocks Unprotected Blocks STATUS Register 0 (low) x Protected Protected Protected 1 (high) 0 Protected Protected Protected 1 (high) 1 Protected Writable Writable x = don’t care |
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