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P89CV51RB2 Datasheet(PDF) 63 Page - NXP Semiconductors |
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P89CV51RB2 Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 76 page ![]() P89CV51RB2_RC2_RD2_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 25 August 2009 63 of 76 NXP Semiconductors P89CV51RB2/RC2/RD2 80C51 with 1 kB RAM, SPI 9.1 Explanation of symbols Each timing symbol used in Figure 29 to Figure 33 has 5 characters. The first character is always a ‘t’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A — Address C — Clock D — Input data H — Logic level HIGH I — Instruction (program memory contents) L — Logic level LOW or ALE P — PSEN Q — Output data R — RD signal T — cycle Time V — Valid W — WR signal X — No longer a valid logic level Z — High impedance (float) Example: tAVLL = Address valid to ALE LOW time tLLPL = ALE LOW to PSEN LOW time Fig 29. External program memory read cycle 002aaa548 port 2 PSEN ALE A0 to A7 tLLAX tPLAZ tPXIZ tLLPL tAVIV tAVLL tLLIV tPLIV tPLPH INSTR IN A8 to A15 A8 to A15 A0 to A7 port 0 tPXIX tPXAV tLHLL |
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