MPC8377E datasheet(75/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

SPI

20.2

SPI AC Timing Specifications

Table 69 provides the SPI input and output AC timing specifications.

Figure 48 provides the AC test load for the SPI.

Figure 48. SPI AC Test Load

Figure 49 through Figure 50 represent the AC timing from Table 69. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Output low voltage

IOL = 8.0 mA

VOL

—0.5

Output low voltage

IOL = 3.2 mA

VOL

—0.4

Table 69. SPI AC Timing Specifications

Parameter

Symbol1

Min

Max

Unit

SPI outputs—Master mode (internal clock) delay

tNIKHOV

0.5

SPI outputs—Slave mode (external clock) delay

tNEKHOV

SPI inputs—Master mode (internal clock) input setup time

tNIIVKH

4—

SPI inputs—Master mode (internal clock)input hold time

tNIIXKH

0—

SPI inputs—Slave mode (external clock) input setup time

tNEIVKH

4—

SPI inputs—Slave mode (external clock) input hold time

tNEIXKH

2—

Note:

1 The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the internal

timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin. The maximum SPICLK input frequency is 66.666 MHz.

Table 68. SPI DC Electrical Characteristics (continued)

Parameter

Condition

Symbol

Min

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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