ATtiny43U-MU datasheet(79/182 Pages) ATMEL

79 / 182 page

8048B–AVR–03/09

12. 8-bit Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1)

12.1

Features

• Two Independent Output Compare Units

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Six Independent Interrupt Sources (TOV0, OCF0A, OCF0B, TOV1, OCF1A, and OCF1B)

12.2

Overview

Timer/Counter0 and Timer/Conter1 are general purpose Timer/Counter modules with two inde-

pendent Output Compare Units, each, and with PWM support. They allow accurate program

execution timing (event management) and wave generation.

the Timer/Counter number, and a lower case “x” replaces the Output Compare Unit, in this case

Compare Unit A or Compare Unit B. However, when using the register or bit defines in a pro-

gram, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value

and so on.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 12-1 on page 79. For

the actual placement of I/O pins, refer to Figure 1-1 on page 2. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the “Register Description” on page 90.

Figure 12-1. 8-bit Timer/Counter Block Diagram

Clock Select

Timer/Counter

OCRnA

OCRnB

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Fixed

TOP

Value

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

TCCRnA

TCCRnB

Edge

Detector

( From Prescaler )

clk

ATtiny43U-MU Datasheet(PDF) 79 Page - ATMEL Corporation

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