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LTM2882 Datasheet(PDF) 13 Page - Linear Technology

Part # LTM2882
Description  Dual Isolated RS232 關Module Transceiver Power
PDF  16 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTM2882 Datasheet(HTML) 13 Page - Linear Technology

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LTM2882
13
2882p
APPLICATIONS INFORMATION
PCB Layout
The high integration of the LTM2882 makes PCB layout
very simple. However, to optimize its electrical isolation
characteristics, EMI, and thermal performance, some lay-
out considerations are necessary. Figure 7 is a suggested
layout for good thermal performance and to optimize
isolation characteristics.
• Under heavily loaded conditions, the current in VCC and
GND can exceed 300mA. PCB copper must be made
wide enough in these paths to ensure resistive losses
do not cause the supply voltage at the LTM2882 to drop
below the minimum allowed levels. Similarly, the metal
in the VCC2 and GND2 must be wide enough to support
any external load connected.
• Input and output decoupling is not required, since
these components are integrated within the package.
If additional capacitance is used, place as close to the
power and ground terminals as possible to minimize
high frequency noise. For EMI sensitive applications,
an additional low ESR capacitance of 6.8μF to 22μF is
recommended from VCC to GND.
• Do not place copper on the PCB between the inner col-
umns of pads. This area must remain open to withstand
the rated isolation voltage. The PCB may also be slotted
in this area to facilitate cleaning and ensure contamina-
tion does not compromise the isolation voltage.
• The recommended layout of Figure 7 shows copper
planes for GND and GND2, which is good practice to
optimize signal fidelity and minimize emissions on either
side of the isolation boundary. However, this creates a
dipole antenna which can radiate differential voltages
formed between GND and GND2. A small capacitance
(<200pF) from GND to GND2, either discrete or embed-
ded within the substrate, provides a low impedance
path minimizing the high frequency differential voltages
and substantially reducing radiated emissions. Care
should be exercised in applying these techniques to
insure the voltage rating of the isolation barrier is not
compromised.
Figure 7. Recommended PCB Layout
VCC
VCC2
VL
ON
DIN
T1IN
R1OUT
T2IN
DE
DOUT
T1OUT
R1IN
T2OUT
R2IN
R2OUT
SLOT
TOP COPPER
GND2
GND
SLOT
BOTTOM COPPER



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