HT93LC86

Rev. 1.40

4

July 10, 2009

Functional Description

The HT93LC86 is accessed via a three-wire serial com-

munication interface. The device is arranged into 1024

words by 16 bits or 2048 words by 8 bits depending

whether the ORG pin is connected to VCC or VSS. The

HT93LC86 contains seven instructions: READ, ERASE,

WRITE, EWEN, EWDS, ERAL and WRAL. When the

user selectable internal organization is arranged into

1024

´16 (2048´8), these instructions are all made up of

13(14) bits data: 1 start bit, 2 op code bits and 10(11) ad-

dress bits.

By using the control signal CS, SK and data input signal

DI, these instructions can be transmitted to the

HT93LC86. These serial instruction data presented at

the DI input will be written into the device on the rising

edge of SK. During the READ cycle, the DO pin acts as

the data output and during the WRITE or ERASE cycle,

the DO pin indicates the BUSY/READY status. When

the DO pin is active for reading data or as a

BUSY/READY indicator the CS pin must be high; other-

wise the DO pin will be in a high-impedance state. For

successful instruction execution, CS must be pulled low

once after the instruction is sent. After power on, the de-

vice is by default in the EWDS state. An EWEN instruc-

tion must be performed before any ERASE or WRITE

instruction can be executed. The following are the func-

tional descriptions and timing diagrams of all seven in-

structions.

READ

The READ instruction will stream out data at a specified

address on the DO pin. The data on DO pin changes

during the low-to-high edge of SK signal. The 8 bit or 16

bit data stream is preceded by a logical

²0² dummy bit.

Irrespective of the condition of the EWEN or EWDS in-

struction, the READ command is always valid and inde-

pendent of these two instructions. After the data word

has been read the internal address will be automatically

incremented by 1 allowing the next consecutive data

word to be read out without entering further address

data. The address will wrap around with CS High until

CS returns to LOW.

EWEN/EWDS

The EWEN/EWDS instruction will enable or disable the

programming capabilities. At both the power on and

power off state the device automatically enters the disable

mode. Before a WRITE, ERASE, WRAL or ERAL instruc-

tion is given, the programming enable instruction EWEN

must be issued, otherwise any ERASE/WRITE instruc-

tions will be invalid. After the EWEN instruction is issued,

the programming enable condition remains until the power

is removed off until an EWDS instruction is issued. No data

can be written into the device in the programming disable

state. By so doing, the internal memory data can be pro-

tected.

ERASE

The ERASE instruction erases data at the specified ad-

dresses in the programming enable mode. After the

ERASE op-code and the specified address have been

issued, the data erase is activated by the falling edge of

CS. Since the internal auto-timing generator provides all

timing signals for the internal erase, the SK clock is not

required. During the internal erase, the busy/ready sta-

tus can be verified by keeping CS high. If busy, the DO

pin will remain low but when the operation is over, the

DO pin will return to a high level permitting further in-

structions to be executed.

WRITE

The WRITE instruction writes data into the device at the

specified addresses in the programming enable mode.

After the WRITE op-code and the specified address and

data have been issued, the data writing is activated by

the falling edge of CS. Since the internal auto-timing

generator provides all timing signal for the internal writ-

ing, the SK clock is not required. The auto-timing write

cycle includes an automatic erase-before-write capabil-

ity. It is therefore not necessary to erase data before the

WRITE instruction is issued. During the internal writing,

the busy/ready status can be verified by keeping CS

high. If busy, the DO pin will remain low but when the

operation is over, the DO pin will return to a high level

permitting further instructions to be executed.

ERAL

The ERAL instruction erases the entire 1024

´16 or

2048

´8 memory cells to a logical ²1² state in the pro-

gramming enable mode. After the erase-all instruction

has been issued, the data erase feature is activated by

the falling edge of CS. Since the internal auto-timing

generator provides all timing signal for the erase-all op-

eration, the SK clock is not required. During the internal

erase-all operation, the busy/ready status can be veri-

fied by keeping CS high. If busy, the DO pin will remain

low but when the operation is over, the DO pin will return

to a high level permitting further instructions to be exe-

cuted.

WRAL

The WRAL instruction writes data into the entire

1024

´16 or 2048´8 memory cells in the programming

enable mode. After the write-all instruction set has been

issued, the data writing is activated by the falling edge of

CS. Since the internal auto-timing generator provides all

timing signals for the write-all operation, the SK clock is

not required. During the internal write-all operation, the

busy/ready status can be verified by keeping CS high. If

busy, the DO pin will remain low but when the operation

is over, the DO pin will return to a high level permitting

further instructions to be executed.