ST7033 datasheet(8/39 Pages) SITRONIX

8 / 39 page

ST7033

Ver 1.1

8/39

2009/07/17

E_RD

Read/Write operation control pin (if using Parallel interface).

MPU Type

E_RD

Interface Mode

6800-series

Signals (Instruction or Data) on

data bus will be latched by MPU

or this IC (depends on R/W) at

the falling edge of this signal.

8080-series

/RD

Internal status (or display data)

will be read out to data bus after

the falling edge of this signal.

D0…D7

Data Bus. If /CSB signal is not actived, D7…D0 are high impedance.

Parallel interface (6800 or 8080):

I/O port which is connected to the standard 8-bit MPU data bus.

Serial SPI interface (3 line or 4 line):

SCLK: D0;

SDA: D1~D3;

D4~D7 must connect to VDD1.

LCD DRIVER SUPPLY

OSC

OSC=”H”: Use the built-in oscillator.

OSC=”L”: Both external clock and built-in oscillator are inhibited. And

the display circuits will not be clocked and kept in a DC state. To

avoid this, the chip should always be put into Power-Down Mode

before stopping the clock.

If using external clock, connect this pin to the external clock.

POWER SUPPLY

VSS

Power

Ground.

VDD1

Power

Digital circuits supply voltage.

The 2 power supply rails, VDD1 and VDD2, could be connected together.

Use this power to be the high voltage level for the Option pins.

VDD2

Power

Analog circuits supply voltage.

The 2 power supply rails, VDD and VDD2, could be connected together.

XV0I, XV0O, XV0S

Power

Supply

Negative LCD driver supply voltages.

XV0I, XV0O & XV0S should be separated in ITO layout.

XV0I, XV0O & XV0S should be connected together in FPC layout.

V0I, V0O, V0S;

VGI, VGO, VGS

Power

Supply

This is a multi-level power supply for the liquid crystal.

≥ VG ≥ VM ≥ VSS ≥ XV0

V0I, V0O & V0S should be separated in ITO layout.

V0I, V0O & V0S should be connected together in FPC layout.

VGI, VGO & VGS should be separated in ITO layout.

VGI, VGO & VGS should be connected together in FPC layout.

Power

Supply

LCD driving voltage for commons.

VRS

Power

Reserved to monitor internal Voltage Regulator reference level, must be left

open.

Configuration Pins

MODE

Test pin.

Must fix to “L”

Set Booster stage.

VSS=4X;

VDD=5X.

ST7033 Datasheet(PDF) 8 Page - Sitronix Technology Co., Ltd.

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