AS3525 datasheet(102/194 Pages) AMSCO

102 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

102

- 194

7.3.14.1 Input clock selection

Input clock is either coming directly from the clk_ext pin or from the internal 24MHz crystal oscillator. Usage of external pin or internal oscillator is

selected by the dedicated pin clk_sel.

Table 85 Clock Selection

Clk_sel

Description

clk_main = clk_int

clk_main = clk_ext

Three main internal clocks are generated as source for all clock dividers for all modules.

•

clk_a, clk_b: the outputs of two independently configurable PLLs.

•

clk_main: this clock is always available without the need of configuring any internal PLL

An important constraint of the system is the memory type of the RAM: the internal 1-TRAM needs refresh cycles, with the following important

restrictions:

•

the free running AHB/APB clock (PCLK) for the 1-TRAM must always be present: also for changing frequency settings, this

must be taken into account (e.g. switch from clk_main to PLL output only after PLL is settled (start-up time).

•

the minimum frequency for the free running AHB/APB clock of the 1-TRAM is 20 MHz.

Important note: Switching between the different frequencies must be done in a pre-defined order using the CGU-driver software.

7.3.14.2 Clock Gating

For all peripheral clock domains clock gating is possible. Clock gating can be enabled/disabled by the corresponding bits within the clock control

register CGU_PERI. After start-up, only the modules, which are necessary for booting the device, are enabled. These enabled peripherals are

•

1-TRAM controller and 1-TRAM macros

•

external memory interface MPMC

•

internal ROM

•

vectored IR controller (VIC)

7.3.14.3 Interrupt generation

An interrupt can be generated after the PLL is locked.

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