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AS3525 Datasheet(PDF) 134 Page - ams AG

Part # AS3525
Description  Advanced Audio Processor System
PDF  194 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3525 Datasheet(HTML) 134 Page - ams AG

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AS3525-A/-B C22O22
Data Sheet, Confidential
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.13
134
- 194
7.4.7
Speaker Output
7.4.7.1
General
The speaker output is designed to provide the stereo audio signal with 2x500mW @ 4
Ω.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from
−40.5dB to
+6dB. The maximum output power of 500mW @ 4
Ω is achieved, by setting the mixer output to 1Vp and using the gain of +6dB.
Figure 51 Speaker Output
Speaker connected via decoupling capacitors
7.4.7.2
Latchup Protection
For latchup protection of pins LSPL and LSPR, external schottky diodes must be implemented from LSPL to BVDD and LSPR to BVDD as drawn in
the above diagram. These diodes protect pins LSPL and LSPR against the back-voltage induced by the inductance of the speaker in case of
switching off the speaker. These diodes must be schottky type diodes with low forward voltages to prevent high current through the internal
LSPR/LSPL ESD protection diodes that potentially would cause latchup for currents exceeding the maximum input current specifications given in
chapter 6.1 Absolute Maximum Ratings.
These schottky diodes must be capable of surging maximum peak currents of up to 600 mA.
7.4.7.3
No-Pop Function
BGND pin, which needs a 100nF capacitor outside, gets charged on power-up to BVDD/2.To avoiding click and pop noise during power-up and
shutdown, the output is automatically set to mute when the output stage is disabled.
The Start-up time before releasing mute is about 100ms. To avoid pop-noise the 150ms discharging time of SPR / SPL after a shutdown (220µF
capacitor in stereo single ended mode assumed), have to be waited before starting up again.
7.4.7.4
Over-current Protection
This output stage has an over-current protection, which disables the output for 0 to 512ms. This value can be set in the speaker registers. The over-
current protection limit of SPR and SPL pin is typical 700mA. To get an interrupt on an over-current event, the corresponding bit in the IRQ_ENRD1
register (0x26h) has to be set.



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