AS3525 datasheet(143/194 Pages) AMSCO

143 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

143

- 194

7.4.10

I2S Digital Audio Interface

7.4.10.1 Input

Digital audio data can be fed into the AS3515A via the I2S interface These input data are then used by the 18-bit DAC to generate the analog audio

signal.

The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –40.5dB to

+6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values. Changing the volume

and mute control can only be done after enabling the input.

7.4.10.2 Output

This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a volume

control to the 14 bit ADC. The digital output is done via an I2S interface.

The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –34.5dB to

+12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume settings are set to their default values. Changing the

volume and mute control can only be done after enabling the input.

The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate.

7.4.10.3 Signal Description

The digital audio interface uses the standard I2S format:

•

left justified

•

MSB first

•

one additional leading bit

The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than 18 bits

sampled, the data sample is completed with “0”s. The ADC output is always 16 bit. If more SCLK pulses are provided, only the first 16 will be

significant. All following bits will be “0”.

SCLK has not to be necessarily synchronous to LRCK but the high going edge has to be separate from LRCK edges. The LRCK signal has to be

derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always in correct phase

lock condition to the external LRCK.

The digital part has to provide MCLK (master clock) with 128*fs (fs = audio sampling frequency) over-sampling to guarantee a proper DAC and

ADC operation.

Figure 55 I2S Left Justified Mode

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