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DM9103 Datasheet(PDF) 21 Page - Davicom Semiconductor, Inc.

Part # DM9103
Description  10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface
PDF  89 Pages
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Manufacturer  DAVICOM [Davicom Semiconductor, Inc.]
Direct Link  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9103 Datasheet(HTML) 21 Page - Davicom Semiconductor, Inc.

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DM9103
3-port switch with PCI Interface
Preliminary datasheet
21
DM9103-DS-P02
September 26, 2007
6.1.7 Subsystem Identification (xxxxxx2cH - PCISID)
Bit
Default
Type
Description
31:16
XXXXH
RO
Subsystem ID
It can be loaded from EEPROM word 1
15:0
XXXXH
RO
Subsystem Vendor ID
It can be loaded from EEPROM word 0
6.1.8 Capabilities Pointer (xxxxxx34H - Cap _Ptr)
Bit
Default
Type
Description
31:8
000000H
RO
Reserved
7:0
01010000
RO
Capability Pointer
The Cap_ Ptr provides an offset (default is 50H) into the function’s PCI
Configuration Space for the location of the first term in the Capabilities Linked List.
The Cap_ Ptr offset is double word aligned so the two least significant bits are
always “0”s
6.1.9 Interrupt & Latency Configuration (xxxxxx3cH - PCIINT)
Bit
Default
Type
Description
31:24
28H
RO
Maximum Latency Timer that can be sustained.
23:16
14H
RO
Minimum Grant
Minimum Length of a Burst Period.
15:8
01H
RO
Interrupt Pin read as 01H to indicate INTA#
7:0
XXH
RW
Interrupt Line that Is routed to the Interrupt Controller
The value depends on system software.
6.1.10 Device Specific Configuration Register (xxxxxx40H- PCIUSR)
Bit
Default
Type
Description
31:30
0
RO
Reserved Bits Read As 0
29
0
RW
When set, enables port 0 or 1 Link Status Change Wake up Event
28
0
RO
Reserved Bit Read As 0
27
0
RW
When set, enables Magic Packet Wake up Event
26
0
RO
When set, indicates the port 0 or 1 Link Change and the Link Status Change Event
occurred
25
0
RO
Reserved Bit Read As 0
24
0
RO
When set, indicates the Magic Packet is received and the Magic packet Event
occurred
23:16
00H
RO
Reserved Bits Read As 0
15:8
00H
RW
Device Specific
7:0
00H
RO
Reserved Bits Read As 0



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