33905 datasheet(23/91 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33904/5

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

LIN 1 AND LIN 2 PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO LIN

PHYSICAL LAYER SPECIFICATION

Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. See Figure 13, page 25.

Duty Cycle 1:

THREC(max) = 0.744 * VSUP

THDOM(max) = 0.581 * VSUP

D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V

0.396

Duty Cycle 2:

THREC(MIN) = 0.422 * VSUP

THDOM(MIN) = 0.284 * VSUP

D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V

0.581

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER

SPECIFICATION

Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds. See Figure 14, page 26.

Duty Cycle 3:

THREC(MAX) = 0.778 * VSUP

THDOM(MAX) = 0.616 * VSUP

D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V

0.417

Duty Cycle 4:

THREC(MIN) = 0.389 * VSUP

THDOM(MIN) = 0.251 * VSUP

D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V

0.590

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE

LIN Fast Slew Rate (Programming Mode)

SRFAST

μs

LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS

VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. See Figure 13, page 25.

Propagation Delay and Symmetry (See Figure 13, page 25 and Figure 14,

page 26)

Propagation Delay of Receiver, tREC_PD=MAX (tREC_PDR, tREC_PDF)

Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR

tREC_PD

tREC_SYM

-2.0

4.2

6.0

2.0

μs

Bus Wake-Up Deglitcher (Low Power VDD OFF and Low Power VDD ON

Modes)

(See Figure 15, page 25 for Low Power VDD OFF Mode and Figure 16,

page 26 for Low Power Mode)

tPROPWL

μs

Bus Wake-up Event Reported

From Low Power VDD OFF Mode

From Low Power VDD ON Mode

tWAKE_LPVDD

OFF

tWAKE_LPVDD

1.0

1500

μs

TXD Permanent Dominant State Delay (guaranteed by design)

tTXDDOM

0.65

1.0

1.35

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions 5.5 V

≤ VSUP ≤ 27 V, -40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

33905 Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc

33905 Datasheet(HTML) 23 Page - Freescale Semiconductor, Inc

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