33905 datasheet(69/91 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33904/5

SERIAL PERIPHERAL INTERFACE

DETAIL OF CONTROL BITS AND REGISTER MAPPING

.REGULATOR, CAN, I/O, INT AND LIN REGISTERS

Table 30. (25)REGULATOR register, REG

MOSI First Byte [15-8]

[b_15 b_14] 01_111 [P/N]

MOSI Second Byte, bits 7-0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

01 01_ 111 P

VAUX[1]

VAUX[0]

5V-can[1]

5V-can[0]

VDD bal en

VDD bal auto

VDD off en

Default state

N/A

Condition for default

POR

Bits

Description

b7 b6

VAUX[1], VAUX[0] - Vauxilary regulator control

Regulator OFF

Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags not reported. VAUX disable in case UV or UV

detected after 1.0ms blanking time.

Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags active. VAUX disable in case UV or UV detected after

1.0ms blanking time.

Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags active. VAUX disable in case UV or UV detected after

μs blanking time.

b4 b3

5V-can[1], 5V-can[0] - 5V-CAN regulator control

Regulator OFF

Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags not reported.

Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags active.

Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags active. 5V-CAN disable

in case UV or UV detected after 25

μs blanking time.

VDD bal en - Control bit to Enable the VDD external ballast transistor

External VDD ballast disable

External VDD ballast Enable

VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typ 60mA

Disable the automatic activation of the external ballast

Enable the automatic activation of the external ballast, if VDD > typ 60mA

VDD off en - Control bit to allow transition into Low Power VDD OFF Mode (to prevent VDD turn OFF)

Disable Usage of Low Power VDD OFF Mode

Enable Usage of Low Power VDD OFF Mode

Notes

25.

The first time the device is set in Normal mode, the CAN is in Sleep wake-up enable (10). The next time the device is set in Normal

mode, the CAN state is controlled by the bit 7 and bit6 states.

33905 Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc

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