P89LPC9151FDH datasheet(10/91 Pages) NXP

10 / 91 page

P89LPC9151_61_71_2

Product data sheet

Rev. 02 — 9 February 2010

10 of 91

NXP Semiconductors

P89LPC9151/9161/9171

8-bit microcontroller with 8-bit ADC

6.2 Pin description

Table 3.

P89LPC9151 Pin description

Symbol

Type

Description

TSSOP14

P0.0 to P0.5

I/O

Port 0: Port 0 is an 6-bit I/O port with a user-configurable output type. During

reset Port 0 latches are configured in the input only mode with the internal pull-up

disabled. The operation of Port 0 pins as inputs and outputs depends upon the

port configuration selected. Each port pin is configured independently. Refer to

Section 7.15.1 “Port configurations” and Table 16 “Static characteristics” for

details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt trigger inputs.

Port 0 also provides various special functions as described below:

P0.0/CMP2/

KBI0

I/O

P0.0 — Port 0 bit 0.

CMP2 — Comparator 2 output

KBI0 — Keyboard input 0.

P0.1/CIN2B/

KBI1/AD10

I/O

P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

AD10 — ADC1 channel 0 analog input.

P0.2/CIN2A/

KBI2/AD11

I/O

P0.2 — Port 0 bit 2.

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

AD11 — ADC1 channel 1 analog input.

P0.3/CIN1B/

KBI3/AD12

I/O

P0.3 — Port 0 bit 3. High current source.

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

AD12 — ADC1 channel 2 analog input.

P0.4/CIN1A/

KBI4/DAC1/AD13

I/O

P0.4 — Port 0 bit 4. High current source.

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

DAC1 — Digital-to-analog converter output 1.

AD13 — ADC1 channel 3 analog input.

P0.5/CMPREF/

KBI5

I/O

P0.5 — Port 0 bit 5. High current source.

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

CLKIN — External clock input.

P1.0 to P1.5

I/O, I

[1]

Port 1: Port 1 is an 6-bit I/O port with a user-configurable output type, except for

three pins as noted below. During reset Port 1 latches are configured in the input

only mode with the internal pull-up disabled. The operation of the configurable

Port 1 pins as inputs and outputs depends upon the port configuration selected.

Each of the configurable port pins are programmed independently. Refer to

Section 7.15.1 “Port configurations” and Table 16 “Static characteristics” for

details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt trigger inputs.

Port 1 also provides various special functions as described below:

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