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VT98521 Datasheet(PDF) 1 Page - Vaishali Semiconductor |
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VT98521 Datasheet(HTML) 1 Page - Vaishali Semiconductor |
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1 / 5 page ![]() 2002-02-25 Page 1 MDST-0017-02 www.vaishali.com Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063 Applications •= Low cost general-purpose clock source General Description The VT98521 is a 3.3V CMOS, clock multiplier integrated circuit. The device provides an excellent quality high frequency output clock from a lower frequency crystal or clock input. Tri-level selection inputs S0 and S1 are used to select any one of eight multipliers, stored in the on-board ROM, and apply it to the input to produce the desired output, up to 220 MHz. Phase Locked Loop (PLL) technology allows the device to use an input signal from an inexpensive crystal. When Output Enable (OE) is low, the clock output is in high impedance state. The VT98521, when used with an inexpensive crystal, provides a cost-effective clock source for most electronic systems. Figure 1. Functional Block Diagram VT98521 3.3V Clock Multiplier Features •= Low phase noise •= Zero ppm multiplication error •= Input clock frequency 5 - 50 MHz. •= Input crystal frequency 5 – 27 MHz •= Output clock frequencies up to 220 MHz. •= 5V-tolerant inputs and output •= Fully Compatible with all popular CPUs •= Duty Cycle - 45/55 up to 160 MHz. - 40/60 160 MHz to 220 MHz •= 25mA drive capability at TTL levels •= High-Z output for board level testing X1/ICLK VDD S0 S1 Output Enable Clock or Xtal input PLL Clock Multiplier & ROM Output Buffer Xtal. Osc. GND X2 Optional caps CLK Figure 2. Pin Assignment 1 2 3 4 8 7 6 5 X1/ICLK VDD GND S1 X2 OE S0 CLK 8-pin SOIC/MSOP |
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