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VG36648041CT Datasheet(PDF) 13 Page - Vanguard International Semiconductor

Part # VG36648041CT
Description  CMOS Synchronous Dynamic RAM
PDF  70 Pages
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Manufacturer  VML [Vanguard International Semiconductor]
Direct Link  http://www.vis.com.tw
Logo VML - Vanguard International Semiconductor

VG36648041CT Datasheet(HTML) 13 Page - Vanguard International Semiconductor

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Document : 1G5-0153
Rev.1
Page 13
VIS
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
2.5 Command Truth Table for CKE Note 1
Note:
Current state
CKE
n - 1
CKE
n
CS
RAS
CAS
WE
Address
Action
Notes
Self refresh
(S.R.)
H
X
X
X
X
X
X
INVALID, CLK (n - 1)would exit S.R.
L
H
H
X
X
X
X
S.R. Recovery
2
L
H
L
H
H
X
X
S.R. Recovery
2
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
Maintain S.R.
Self refresh
recovery
H
H
H
X
X
X
X
Idle after tRC
H
H
L
H
H
X
X
Idle after tRC
H
H
L
H
L
X
X
ILLEGAL
H
H
L
L
X
X
X
ILLEGAL
H
L
H
X
X
X
X
Begin clock suspend next cycle
5
H
L
L
H
H
X
X
Begin clock suspend next cycle
5
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
H
X
X
X
X
X
Exit clock suspend next cycle
2
L
L
X
X
X
X
X
Maintain clock suspend
Power down
(P.D.)
H
X
X
X
X
X
INVALID, CLK (n - 1) would exit P.D.
L
H
X
X
X
X
X
EXIT P.D.
Idle
2
L
L
X
X
X
X
X
Maintain power down mode
Both banks
idle
H
H
H
X
X
X
Refer to operations in Operative
Command Table
H
H
L
H
X
X
Refer to operations in Operative
Command Table
H
H
L
L
H
X
Refer to operation in Operative
Command Table
H
H
L
L
L
H
X
Auto Refresh
H
H
L
L
L
L
Op - Code Refer to operations in Operative
Command Table
H
L
H
X
X
X
Refer to operations in Operative
Command Table
H
L
L
H
X
X
Refer to operations in Operative
Command Table
H
L
L
L
H
X
Refer to operations in Operative
Command Table
H
L
L
L
L
H
X
Self refresh
3
H
L
L
L
L
L
Op - Code Refer to operations in Operative
Command Table
L
X
X
X
X
X
X
Power down
3
Any state
other than
listed above
H
H
X
X
X
X
X
Refer to operations in Operative
Command Table
H
L
X
X
X
X
X
Begin clock suspend next cycle
4
L
H
X
X
X
X
X
Exit clock suspend next cycle
L
L
X
X
X
X
X
Maintain clock suspend
→
1. H : Hight level, L : low level, X : High or low level (Don't care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSREX is not satisfied.



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