ICS9220B

Programmable Rambus

TM

XDR

TM

Clock Generator

DATASHEET

1

General Description

Features

The ICS9220 clock generator provides Programmable clock

signals to support the Rambus XDR

and Redwood logic interface. The ICS9220 has been

optimized for 100MHz reference input that may or may not be

modulated for spread spectrum. The ICS9220 provides 2

differential clock pairs in a space saving 28-pin TSSOP

package and provides an off-the-shelf high-performance

interface solution.

Figure 1 shows the major components of the ICS9220 XDR

Clock Generator.

These include the a PLL, a Bypass

Multiplexer and two differential output buffers. The outputs

can be disabled by a logic low on the OE pin. An output is

enabled by the combination of the OE pin being high, and 1

in its SMBus Output control register bit.

The PLL receives a reference clock, CLK_INT/C and outputs

a clock signal at a frequency equal to the input frequency

times a multiplier. Table 2 shows the multipliers selectable

via the SMBus interface. This clock signal is then fed to the

differential output buffers to drive the enabled clocks. Disabled

outputs are set to Hi-Z. The Bypass mode routes the input

clock, CLK_INT/C, directly to the differential output buffers,

bypassing the PLL.

Up to four ICS9220 devices can be cascaded on the same

SMBus.Table 3 shows the SMBus addressing and control for

the four devices.

Block Diagram

•

300 - 700 MHz clock source

•

2 open-drain differential output drives with short

term jitter < 40ps

•

Spread spectrum compatible

•

Reference clock is differential or single-ended

100MHz

•

SMBus programmability for:

- frequency multiplier

- output enable

- operating mode

•

Support systems where XDR subsystem is

asynchronous to other system clocks

•

2.5V power supply

PLL

Bypass

MUX

RegA

RegB

CLK_INT

CLK_INC

SMBCLK

OE

OE

OE

BYPASS#/PLL

SMBDAT

AS1

AS2

ODCLK_C1

ODCLK_T1

ODCLK_C0

ODCLK_T0

Pin Configuration

AVDD2.5

1

28 VDD2.5

AGND

2

27 GND

IREFY

3

26 GND

AGND

4

25 ODCLK_T0

CLK_INT

5

24 ODCLK_C0

CLK_INC

6

23 GND

VDD2.5

7

22 VDD2.5

GND

8

21 VDD2.5

SMBCLK

9

20 GND

SMBDAT 10

19 ODCLK_T1

OE 11

18 ODCLK_C1

AS1 12

17 GND

AS2 13

16 GND

BYPASS#/PLL 14

15 VDD2.5

28-Pin 4.4mm TSSOP