| Electronic Components Datasheet Search |
|
ICS9220B Datasheet(PDF) 10 Page - Integrated Device Technology |
|
|
|||||||||||||||||||||||||||||
ICS9220B Datasheet(HTML) 10 Page - Integrated Device Technology |
|
10 / 16 page ![]() 1427A—01/26/10 ICS9220B Programmable Rambus TM XDRTMClock Generator 10 IDTTM Programmable RambusTM XDRTMClock Generator DC Characteristics - Inputs TA = -40°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) SYMBOL CONDITIONS MIN TYP MAX UNITS VDD2.5, AVDD 2.375 2.625 V VIHCLK 0.6 0.95 V VILCLK -0.15 0.15 V VIXCLK 0.2 0.55 V VIXCLK 0.15 V VTH 0.35 0.5VDD2.5 V VIHSE VTH + 0.3 2.625 V VILSE -0.15 VTH - 0.3 V VIH 1.4 2.625 V VIL -0.15 0.8 V VIHSMB 1.4 3.465 2 V VILSMB -0.15 0.8 V Notes: 1 2 When using singled-ended clock input, VTH is supplied to CLK_INTC as shown in Figure 2. Duty cycle of singled-ended CLK_IN is measured at VTH. This range of SMBus input high voltages allows the 9220 to co-exist with 3.3V, 2.5V and 1.8V devices on the same SMBus. PARAMETER Supply Voltage High-level input voltage Low-level input voltage Crossing point voltage Difference in crossing point voltage Input threshold voltage High-level input voltage for single-ended CLK_IN Low-level input voltage - SMBus CLK_INT, CLK_INC Singled-ended CLK_IN 1 OE, AS1, AS2, BYPASS#/PLL SMBCLK, SMBDAT Low-level input voltage for single-ended CLK_IN High-level input voltage Low-level input voltage High-level input voltage - SMBus SYMBOL CONDITION MIN TYP MAX UNITS f = 400 to 635 MHz -40 ps f = 635 to 800 MHz -30 ps Tjcyc-cyc 100 ps DC 45 55 % tR, tF 20% to 80% of output voltage 140 300 ps tR-F 20% to 80% of output voltage - 100 ps ZOUT 2 VOL = 0.9 V 1000 - Ω Notes: 1 2 AC Characteristics-Outputs PARAMETER 1 Cycle-to-cycle Jitter Duty cycle Short term jitter (over 1 to 6 clock cycles) Guaranteed by design and characterization, not 100% tested in production Zout is defined at the output pins. Dynamic output impedance TA = -40°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 5% (unless otherwise stated) Output rise and fall times Difference between output rise and fall time on same pin of a single device tJ 2 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |