AMPL138ZCEA3 datasheet(81/268 Pages) TI

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2000 N

Max PLL Lock Time =

where N = Pre-Divider Ratio

M = PLL Multiplier

6.6.2

Device Clock Generation

OMAP-L138 Low-Power Applications Processor

www.ti.com

SPRS586A – JUNE 2009 – REVISED AUGUST 2009

Table 6-4. Allowed PLL Operating Conditions (PLL0 and PLL1)

Default

NO.

PARAMETER

MIN

MAX

UNIT

Value

PLLRST: Assertion time during initialization

N/A

1000

N/A

Lock time: The time that the application has to

wait for the PLL to acquire lock before setting

OSCIN

N/A

PLLEN, after changing PREDIV, PLLM, or

cycles

OSCIN

PREDIV: Pre-divider value

/32

PLLREF: PLL input frequency

MHz

PLLM: PLL multiplier values

x20

x32

PLLOUT: PLL output frequency

N/A

400

600(1)

MHz

POSTDIV: Post-divider value

/2(1)

/32

(1)

PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL

output clock.

PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1

manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are

responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock

inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks

from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test

points.

PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the mDDR/DDR2

Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or

peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency

scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on

the application requirements. In addition, some peripherals have specific clock options independent of the

ASYNC clock domain.

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