AMPL138ZCEA3 datasheet(2/268 Pages) TI

2 / 268 page

OMAP-L138 Low-Power Applications Processor

SPRS586A – JUNE 2009 – REVISED AUGUST 2009

www.ti.com

–

RMII Reduced Media Independent Interface

With Multiple Chip-Selects

–

Management Data I/O (MDIO) Module

• Two Multimedia Card (MMC)/Secure Digital

• Video Port Interface (VPIF):

(SD) Card Interface with Secure Data I/O

(SDIO) Interfaces

–

Two 8-bit SD (BT.656), Single 16-bit or

Single Raw (8-/10-/12-bit) Video Capture

• Two Master/Slave Inter-Integrated Circuit (I2C

Channels

Bus™)

–

Two 8-bit SD (BT.656), Single 16-bit Video

• One Host-Port Interface (HPI) With 16-Bit-Wide

Display Channels

Muxed Address/Data Bus For High Bandwidth

• Universal Parallel Port (uPP):

• Programmable Real-Time Unit Subsystem

–

High-Speed Parallel Interface to FPGAs and

(PRUSS)

Data Converters

–

Two Independent Programmable Realtime

–

Data Width on Each of Two Channels is 8-

Unit (PRU) Cores

to 16-bit Inclusive

• 32-Bit Load/Store RISC architecture

–

Single Data Rate or Dual Data Rate

• 4K Byte instruction RAM per core

Transfers

• 512 Bytes data RAM per core

–

Supports Multiple Interfaces with START,

• PRU Subsystem (PRUSS) can be

ENABLE and WAIT Controls

disabled via software to save power

• Serial ATA (SATA) Controller:

• Register 30 of each PRU is exported

–

Supports SATA I (1.5 Gbps) and SATA II

from the subsystem in addition to the

(3.0 Gbps)

normal R31 output of the PRU cores.

–

Supports all SATA Power Management

–

Standard power management mechanism

Features

• Clock gating

–

Hardware-Assisted Native Command

• Entire subsystem under a single PSC

Queueing (NCQ) for up to 32 Entries

clock gating domain

–

Supports Port Multiplier and

–

Dedicated interrupt controller

Command-Based Switching

–

Dedicated switched central resource

• Real-Time Clock With 32 KHz Oscillator and

• USB 1.1 OHCI (Host) With Integrated PHY

Separate Power Rail

(USB1)

• Three 64-Bit General-Purpose Timers

• USB 2.0 OTG Port With Integrated PHY (USB0)

(Configurable as Two 32-Bit Timers)

–

USB 2.0 High-/Full-Speed Client

• One 64-Bit General-Purpose Timer (Watch

–

USB 2.0 High-/Full-/Low-Speed Host

Dog)

–

End Point 0 (Control)

• Two Enhanced Pulse Width Modulators

–

End Points 1,2,3,4 (Control, Bulk, Interrupt

(eHRPWM):

or ISOC) Rx and Tx

–

Dedicated 16-Bit Time-Base Counter With

• One Multichannel Audio Serial Port:

Period And Frequency Control

–

Transmit/Receive Clocks up to 50 MHz

–

6 Single Edge, 6 Dual Edge Symmetric or 3

–

Two Clock Zones and 16 Serial Data Pins

Dual Edge Asymmetric Outputs

–

Supports TDM, I2S, and Similar Formats

–

Dead-Band Generation

–

DIT-Capable

–

PWM Chopping by High-Frequency Carrier

–

FIFO buffers for Transmit and Receive

–

Trip Zone Input

• Two Multichannel Buffered Serial Ports:

• Three 32-Bit Enhanced Capture Modules

–

Transmit/Receive Clocks up to 50 MHz

(eCAP):

–

Two Clock Zones and 16 Serial Data Pins

–

Configurable as 3 Capture Inputs or 3

Auxiliary Pulse Width Modulator (APWM)

–

Supports TDM, I2S, and Similar Formats

outputs

–

AC97 Audio Codec Interface

–

Single Shot Capture of up to Four Event

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Telecom Interfaces (ST-Bus, H100)

Time-Stamps

–

128-channel TDM

• 361-Ball Pb-Free Plastic Ball Grid Array

–

FIFO buffers for Transmit and Receive

(PBGA) [ZCE Suffix], 0.65-mm Ball Pitch

• 10/100 Mb/s Ethernet MAC (EMAC):

• 361-Ball Pb-Free Plastic Ball Grid Array

–

IEEE 802.3 Compliant

(PBGA) [ZWT Suffix], 0.80-mm Ball Pitch

–

MII Media Independent Interface

OMAP-L138 Low-Power Applications Processor

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