LM75A_4

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 04 — 10 July 2007

7 of 24

NXP Semiconductors

LM75A

Digital temperature sensor and thermal watchdog

read a register that is different from the one that has been recently read, the pointer byte

must be included. However, a write to the LM75A must always include the pointer byte in

the statement. The bus communication protocols are described in Section 7.10.

At power-up, the Pointer value is equal to 0 and the Temp register is selected; users can

then read the Temp data without specifying the pointer byte.

7.4.2 Configuration register

The Configuration register (Conf) is a write/read register and contains an 8-bit

non-complement data byte that is used to configure the device for different operation

conditions. Table 8 shows the bit assignments of this register.

7.4.3 Temperature register

The Temperature register (Temp) holds the digital result of temperature measurement or

monitor at the end of each analog-to-digital conversion. This register is read-only and

contains two 8-bit data bytes consisting of one Most Significant Byte (MSByte) and one

Least Significant Byte (LSByte). However, only 11 bits of those two bytes are used to store

the Temp data in 2’s complement format with the resolution of 0.125

°C. Table 9 shows the

bit arrangement of the Temp data in the data bytes.

Table 8.

Conf register

Legend: * = default value.

Bit

Symbol

Access Value Description

B[7:5]

reserved

R/W

000*

reserved for manufacturer’s use; should be kept as

zeroes for normal operation

B[4:3]

OS_F_QUE[1:0] R/W

OS fault queue programming

00*

queue value = 1

01

queue value = 2

10

queue value = 4

11

queue value = 6

B2

OS_POL

R/W

OS polarity selection

0*

OS active LOW

1

OS active HIGH

B1

OS_COMP_INT R/W

OS operation mode selection

0*

OS comparator

1

OS interrupt

B0

SHUTDOWN

R/W

device operation mode selection

0*

normal

1

shutdown

Table 9.

Temp register

MSByte

LSByte

7654321076543210

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

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