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LPC1759 Datasheet(PDF) 5 Page - NXP Semiconductors

Part # LPC1759
Description  32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
PDF  64 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC1759 Datasheet(HTML) 5 Page - NXP Semiconductors

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LPC1759_58_56_54_52_51_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 26 January 2010
5 of 64
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
5.
Block diagram
Grey-shaded blocks represent peripherals with connection to the GPDMA.
Fig 1.
Block diagram
SRAM
64/32/
16/8 kB
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
FLASH
ACCELERATOR
FLASH
512/256/128/64/32 kB
DMA
CONTROLLER
ETHERNET
CONTROLLER
WITH DMA(2)
USB HOST/
DEVICE/OTG
CONTROLLER
WITH DMA(4)
I-code
bus
D-code
bus
system
bus
AHB TO
APB
BRIDGE 0
HIGH-SPEED
GPIO
AHB TO
APB
BRIDGE 1
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTAL1
XTAL2
RESET
clocks and
controls
JTAG
interface
debug
port
USB PHY
SSP0
UART2/3
I2S(1)
I2C2
RI TIMER
TIMER2/3
EXTERNAL INTERRUPTS
SYSTEM CONTROL
MOTOR CONTROL PWM
QUADRATURE ENCODER
SSP1
UART0/1
CAN1/CAN2(1)
I2C1
SPI0
TIMER 0/1
WDT
PWM1
12-bit ADC
PIN CONNECT
GPIO INTERRUPT CONTROL
RTC
BACKUP REGISTERS
32 kHz
OSCILLATOR
APB slave group 1
APB slave group 0
DAC(3)
RTC POWER DOMAIN
LPC1759/58/56/54/52/51
master
master
master
002aae153
slave
slave
slave
slave
ROM
slave
slave
MULTILAYER AHB MATRIX
P0, P1,
P2, P4
SDA2
SCL2
SCK0
SSEL0
MISO0
MOSI0
SCK1
SSEL1
MISO1
MOSI1
RXD2/3
TXD2/3
PHA, PHB
INDEX
EINT0
AOUT
MCOA[2:0]
MCOB[2:0]
MCI[2:0]
4
× MAT2
2
× MAT3
1
× I2SRX
3
× I2STX
TX_MCLK
RX_MCLK
RTCX1
RTCX2
VBAT
PWM1[6:1]
2
× MAT0/1
1
× CAP0,
2
× CAP1
RD1/2
TD1/2
SDA1
SCL1
AD0[7:2]
SCK/SSEL
MOSI/MISO
8
× UART1
RXD0/TXD0
P0, P2
PCAP1[1:0]
RMII pins
USB pins
(1) LPC1759/58/56 only
(2) LPC1758 only
(3) LPC1759/58/56/54 only
(4) LPC1752/51 USB device only



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