P89LPC970FDH datasheet(29/66 Pages) NXP

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P89LPC97X_2

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Product data sheet

Rev. 02 — 27 April 2010

29 of 66

NXP Semiconductors

P89LPC970/971/972

8-bit microcontroller with accelerated two-clock 80C51 core

7.18 Reset

The P1.5/RST pin can function as either a LOW-active reset input or as a digital input,

P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin

always functions as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on sequence as this will keep the device in reset.

After power-up this pin will function as defined by the RPE bit. Only a power-up reset will

temporarily override the selection defined by RPE bit. Other sources of reset will not

override the RPE bit.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user configured via UCFG1)

• Power-on detect

• Brownout detect

• Watchdog timer

• Software reset

• UART break character detect reset

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read

this register to determine the most recent reset source. These flag bits can be cleared in

software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:

• During a power-on reset, both POF and BOF are set but the other flag bits are

cleared.

• A Watchdog reset is similar to a power-on reset, both POF and BOF are set but the

other flag bits are cleared.

• For any other reset, previously set flag bits that have not been cleared will remain set.

7.18.1 Reset vector

Following reset, the P89LPC970/971/972 will fetch instructions from either address 0000H

or the Boot address. The Boot address is formed by using the boot vector as the high byte

of the address and the low byte of the address = 00H.

The boot address will be used if a UART break reset occurs, or the non-volatile boot

status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC970/971/972 User manual). Otherwise, instructions will be fetched from address

0000H.

7.19 Timers/counters 0 and 1

The P89LPC970/971/972 has two general purpose counter/timers which are upward

compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to

operate either as timers or event counters. An option to automatically toggle the T0 or T1

pins upon timer overflow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

P89LPC970FDH Datasheet(PDF) 29 Page - NXP Semiconductors

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