PCIMX258CJM4A datasheet(104/144 Pages) FREESCALE

104 / 144 page

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 3

104

Freescale Semiconductor

3.7.17

Synchronous Serial Interface (SSI) Timing

The following subsections describe SSI timing in four cases:

•

Transmitter with external clock

•

Receiver with external clock

•

Transmitter with internal clock

•

Receiver with internal clock

3.7.17.1

SSI Transmitter Timing with Internal Clock

Figure 78 shows the timing for SSI transmitter with internal clock, and Table 79 describes the timing

parameters (SS1–SS52).

Figure 78. SSI Transmitter with Internal Clock Timing Diagram

Table 78. SLCDC Parallel Interface Timing Parameters

Symbol

Parameter

Min.

Typ.

Max.

Units

tcyc

Parallel clock cycle time

78 (

±) tprop

—

4923

tds

Data setup time

(tcyc / 2) (±) tprop

——

—

tdh

Data hold time

(tcyc / 2) (±) tprop

——

—

trss

(tcyc / 2) (±) tprop

——

—

trsh

(tcyc / 2) (±) tprop

——

—

SS19

AUDn_TXC

AUDn_TXFS (bl)

AUDn_TXFS (wl)

SS1

AUDn_TXD

AUDn_RXD

SS2

SS4

SS3

SS5

SS6

SS8

SS10

SS12

SS14

SS18

SS15

SS17

SS16

SS43

SS42

Note: SRXD Input in Synchronous mode only

(Output)

(Input)

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