PCA9554DB datasheet(10/30 Pages) NXP

10 / 30 page

PCA9554_9554A_7

Product data sheet

Rev. 07 — 13 November 2006

10 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

6.5 Device address

6.6 Bus transactions

Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown

in Figure 12 and Figure 13. Data is read from the PCA9554/PCA9554A registers using

the Read mode as shown in Figure 14 and Figure 15. These devices do not implement an

auto-increment function, so once a command byte has been sent, the register which was

addressed will continue to be accessed by reads until a new command byte has been

sent.

Fig 10. PCA9554 device address

Fig 11. PCA9554A device address

002aac494

A0 R/W

fixed

slave address

hardware

selectable

002aac495

A0 R/W

fixed

slave address

programmable

Fig 12. Write to Output Port register

A2 A1 A0

START condition

R/W

acknowledge

from slave

002aac472

acknowledge

from slave

SCL

SDA

write to port

data out

from port

tv(Q)

command byte

acknowledge

from slave

data to port

DATA 1

slave address

0000001

STOP

condition

data 1 valid

Fig 13. Write to Conﬁguration register or Polarity Inversion register

A2 A1 A0

START condition

R/W

acknowledge

from slave

002aac473

acknowledge

from slave

SCL

SDA

data to

command byte

acknowledge

from slave

data to register

DATA

slave address

000001 1/0

STOP

condition

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