TMS320DM368ZCE datasheet(71/208 Pages) TI

71 / 208 page

TMS320DM368

www.ti.com

SPRS668A – APRIL 2010

System Interconnect

The device uses a 64-bit crossbar architecture to control access between device processors, subsystems

and peripherals. There are eleven transfer masters (TCs have separate read and write connections)

connected to the crossbar; ARM, the Video Processing Subsystem (VPSS), the master peripherals (USB,

EMAC, HPI), and four EDMA transfer controllers. These can be connected to seven separate slave ports;

ARM, the DDR EMIF, CFG bus peripherals, MJCP, and HDVICP. Not all masters may connect to all

slaves. Connection paths are indicated by

√ at intersection points shown in Table 4-1.

Table 4-1. System Connection Matrix

SLAVE MODULE

DMA

ARM Internal

MPEG/JPEG

HD Video Image

Config Bus Registers

DDR EMIF

Master

Memory

Coprocessor

and

Memory

ARM

√

VPSS

√

DMA Master Peripherals

√

(USB, EMAC, HPI)

EDMA3TC0

√

EDMA3TC1

√

EDMA3TC2

√

EDMA3TC3

√

System Interconnect

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