Rev 1.00

March 22, 2010

14

HT45B0K

SPI to USB Bridge

0: the data transfer from the endpoint FIFO to the MCU

(MCU read data from the endpoint FIFO).

1: the data transfer from the MCU to the endpoint FIFO

(MCU write data to the endpoint FIFO).

This bit defines the direction of data transfer between the MCU and the endpoint FIFO.

When the TX bit is set to high, this means that the MCU desires to write data to the

endpoint FIFO. After the MCU write operation has been complete, this bit has to be

cleared to zero before terminating FIFO request to indicate the end of data transfer. For

a MCU read operation, this bit has to be cleared to zero to show that the MCU desires

to read data from the endpoint FIFO and has to be set to high before terminating FIFO

request to indicate the end of data transfer after the completion of MCU read operation.

Bit 0

REQUEST: FIFO request control

0: no operation.

1: Request the desired FIFO.

This bit is used to request the operation of the desired FIFO. After selecting the desired

endpoint, the FIFO can be requested by setting this bit to high. After completion, this bit

has to be cleared to zero.

The MCU can communicate with the endpoint FIFO by setting the corresponding registers, whose

addresses are listed in the following table. After reading the current data, the next data will show

after 2μs, used to check the endpoint FIFO status and responds to the MISC register, if a read/write

action is still being implemented.

Some timing constrains are listed here. By setting the MISC register, the MCU can perform

reading, writing and clearing actions. There are some examples shown in the following for the

endpoint FIFO reading, writing and clearing.

Read or Write FIFOn Table (n=0~5)

Actions

MISC Setting Flow and Status

Check whether FIFOn can be read or not

00H → 01H → delay 2μs, check 41H (ready) or 01H (not

ready) → 00H.

Check whether FIFOn can be written or not

02H → 03H → delay 2μs, check 43H (ready) or 03H (not

ready) → 02H.

Read FIFOn sequence

00H → 01H → delay 2μs, check 41H → read* from

FIFOn register and check not ready (01H) → 03H →

02H.

Write FIFOn sequence

02H → 03H → delay 2μs, check 43H → write* to FIFOn

register and check not ready (03H) → 01H → 00H.

Read 0-sized packet sequence from FIFO0

00H → 01H → delay 2μs, check 81H → clear LEN0 (01H)

→ 03H → 02H.

Write 0-sized packet sequence to FIFOn

02H → 03H → delay 2μs → 01H → 00H.

Note *: There are 2μs existing between 2 reading actions or between 2 writing actions.

R E Q U E S T

R E A D Y

T X

R e a d F I F O T i m i n g

R E Q U E S T

R E A D Y

T X

W r i t e F I F O T i m i n g