In each case the SPI registers require 5 bits. The table below is a summary of all allowed configurations.

MSB

LSB

Gain_1

Gain_0

EN_CL

Null_SW

Hi_Z

Gain Value

(V/V)

Mode of Operation

0

0

0

0

0

0.096

Attenuation Mode

0

1

0

0

0

0.192

Attenuation Mode

1

0

0

0

0

0.384

Attenuation Mode

1

1

0

0

0

0.768

Attenuation Mode

1

0

1

0

0

1

Amplification Mode

1

1

1

0

0

2

Amplification Mode

x

x

x

x

1

–

High Impedance Output

x

x

x

1

0

1

Null Switch Mode

Daisy Chain

The LMP7312 supports daisy chaining of the serial data

stream between multiple chips. To use this feature serial data

is clocked into the first chip SDI pin, and the next chip SDI pin

is connected to the SDO pin of the first chip. Both chips may

share a chip select signal, or the second chip can be enabled

separately. When the chip select pin goes low on both chips

and 5 bits have been clocked into the first chip the next 5 clock

cycle begins moving new configuration data into the second

chip. With a full 10 clock cycles both chips have valid data and

the chip select pin of both chips should be brought high to

prevent the data from overshooting.

30075511

FIGURE 6. Daisy chain

Shared 4-wire SPI with ADC

The LMP7312 is a good choice when interfacing to differential

analog to digital converters ADC141S626 and ADC161S626

of PowerWise® Family. Its SPI interface has been designed

to enable sharing CSB with the ADC. LMP7312 register ac-

cess happens only when CSB is asserted low while SCK is

high. However, the ADC starts conversion under any of the

following conditions: (1) CSB goes low while SCK is high, (2)

CSB goes low while SCK is low, (3) CSB and SCK both going

low. Therefore, if a system uses timing condition #2 above,

LMP7312 and ADC1x1S626 can share CSB and SCK as

shown in Figure 7. The only side-effect would be that writing

to LMP7312 triggers an ADC conversion, but then the result

can be ignored. At other times, the LMP7312 is not affected

by the CSB assertions used to initiate normal ADC conver-

sions.

30075512

FIGURE 7. 4-wire SPI with ADC interface

17

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