HCS12 datasheet(404/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

404

Freescale Semiconductor

B.3 Source Code Compatibility

Every M68HC11 instruction mnemonic and source code statement can be

assembled directly with a CPU12 assembler with no modifications.

The CPU12 supports all M68HC11 addressing modes and includes several

new variations of indexed addressing mode. CPU12 instructions affect

condition code bits in the same way as M68HC11 instructions.

CPU12 object code is similar to but not identical to M68HC11 object code.

Some primary objectives, such as the elimination of the penalty for using Y,

could not be achieved without object code differences. While the object

code has been changed, the majority of the opcodes are identical to those

of the M6800, which was developed more than 20 years earlier.

The CPU12 assembler automatically translates a few M68HC11 instruction

mnemonics into functionally equivalent CPU12 instructions. For example,

the CPU12 does not have an increment stack pointer (INS) instruction, so

the INS mnemonic is translated to LEAS 1,S. The CPU12 does provide

single-byte DEX, DEY, INX, and INY instructions because the LEAX and

LEAY instructions do not affect the condition codes, while the M68HC11

instructions update the Z bit according to the result of the decrement or

increment.

Table B-1 shows M68HC11 instruction mnemonics that are automatically

translated into equivalent CPU12 instructions. This translation is performed

by the assembler so there is no need to modify an old M68HC11 program

to assemble it for the CPU12. In fact, the M68HC11 mnemonics can be used

in new CPU12 programs.

Table B-1. Translated M68HC11 Mnemonics

M68HC11

Mnemonic

Equivalent

CPU12 Instruction

Comments

ABX

ABY

LEAX B,X

LEAY B,Y

Since CPU12 has accumulator offset indexing,

ABX and ABY are rarely used in new CPU12

programs. ABX is one byte on M68HC11 but

ABY is two bytes. The LEA substitutes are two

bytes.

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