Block Guide — S12BDM V4

26

compared to the serial communication rate. This protocol allows a great flexibility for the POD designers,

since it does not rely on any accurate time measurement or short response time to any event in the serial

communication.

Figure 4-5 Target Acknowledge Pulse (ACK)

NOTE:

If the ACK pulse was issued by the target, the host assumes the previous command

was executed. If the CPU enters WAIT or STOP prior to executing a hardware

command, the ACK pulse will not be issued meaning that the BDM command was

not executed. After entering wait or stop mode, the BDM command is no longer

pending.

Figure 4-6 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE

instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the

address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed

(free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the

BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved.

After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the

form of a word and the host needs to determine which is the appropriate byte based on whether the address

was odd or even.

Figure 4-6 Handshake Protocol at Command Level

16 CYCLES

BDM CLOCK

(TARGET MCU)

TARGET

TRANSMITS

PULSE

ACK

HIGH-IMPEDANCE

BKGD PIN

MINIMUM DELAY

FROM THE BDM COMMAND

32 CYCLES

EARLIEST

START OF

NEXT BIT

SPEEDUP PULSE

16th TICK OF THE

LAST COMMAD BIT

HIGH-IMPEDANCE

READ_BYTE

BDM ISSUES THE

BKGD PIN

BYTE ADDRESS

BDM EXECUTES THE

READ_BYTE COMMAND

HOST

TARGET

HOST

TARGET

BDM DECODES

THE COMMAND

ACK PULSE (OUT OF SCALE)

HOST

TARGET

(2) BYTES ARE

RETRIEVED

NEW BDM

COMMAND