Block Guide — S12BDM V4

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Upon detecting the SYNC request from the host, the target performs the following steps:

1.

Discards any incomplete command received or bit retrieved.

2. Waits for BKGD to return to a logic one.

3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.

4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.

5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.

6.

Removes all drive to the BKGD pin so it reverts to high impedance.

The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed

for subsequent BDM communications. Typically, the host can determine the correct communication speed

within a few percent of the actual target speed and the communication protocol can easily tolerate speed

errors of several percent.

As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is

discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the

SYNC response, the target will consider the next negedge (issued by the host) as the start of a new BDM

command or the start of new SYNC request.

Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the

same as in a regular SYNC command. Note that one of the possible causes for a command to not be

acknowledged by the target is a host-target synchronization problem. In this case, the command may not

have been understood by the target and so an ACK response pulse will not be issued.

4.10 Instruction Tracing

When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM

firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to

return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the

TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or

tracing through the user code one instruction at a time.

If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but

no user instruction is executed. Once back in standard BDM firmware execution, the program counter

points to the first instruction in the interrupt service routine.