PIC16F610-ESLASHML datasheet(47/214 Pages) MICROCHIP

47 / 214 page

DS41288F-page 47

PIC16F610/616/16HV610/616

TABLE 5-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

OPTION_REG: OPTION REGISTER

R/W-1

RAPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

RAPU: PORTA Pull-up Enable bit

= PORTA pull-ups are disabled

= PORTA pull-ups are enabled by individual PORT latch values

bit 6

INTEDG: Interrupt Edge Select bit

= Interrupt on rising edge of INT pin

= Interrupt on falling edge of INT pin

bit 5

T0CS: TMR0 Clock Source Select bit

= Transition on T0CKI pin

= Internal instruction cycle clock (FOSC/4)

bit 4

T0SE: TMR0 Source Edge Select bit

= Increment on high-to-low transition on T0CKI pin

= Increment on low-to-high transition on T0CKI pin

bit 3

PSA: Prescaler Assignment bit

= Prescaler is assigned to the WDT

= Prescaler is assigned to the Timer0 module

bit 2-0

PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

BIT VALUE

TMR0 RATE

WDT RATE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

TMR0

Timer0 Modules Register

xxxx xxxx uuuu uuuu

INTCON

GIE

PEIE

T0IE

INTE

RAIE

T0IF

INTF

RAIF

0000 0000 0000 0000

OPTION_REG

RAPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111 1111 1111

TRISA

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the

Timer0 module.

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