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PIC16F610-E/ML Datasheet(PDF) 16 Page - Microchip Technology |
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PIC16F610-E/ML Datasheet(HTML) 16 Page - Microchip Technology |
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16 / 214 page  PIC16F610/616/16HV610/616 DS41288F-page 16 © 2009 Microchip Technology Inc. TABLE 2-1: PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 24, 116 01h TMR0 Timer0 Module’s Register xxxx xxxx 45, 116 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 24, 116 03h STATUS IRP(1) RP1(1) RP0 TO PD ZDC C 0001 1xxx 18, 116 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 24, 116 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 33, 116 06h — Unimplemented — — 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx 00xx 42, 116 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 24, 116 0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 20, 116 0Ch PIR1 —ADIF(2) CCP1IF(2) C2IF C1IF —TMR2IF(2) TMR1IF -000 0-00 22, 116 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 49, 116 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 49, 116 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 52, 116 11h TMR2(2) Timer2 Module Register 0000 0000 55, 116 12h T2CON(2) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 56, 116 13h CCPR1L(2) Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 86, 116 14h CCPR1H(2) Capture/Compare/PWM Register 1 High Byte xxxx xxxx 86, 116 15h CCP1CON(2) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 85, 116 16h PWM1CON(2) PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 85, 116 17h ECCPAS(2) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 102, 116 18h — Unimplemented — — 19h VRCON C1VREN C2VREN VRR FVREN VR3 VR2 VR1 VR0 0000 0000 72, 116 1Ah CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 62, 116 1Bh CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 63, 116 1Ch CM2CON1 MC1OUT MC2OUT — T1ACS C1HYS C2HYS T1GSS C2SYNC 00-0 0010 65, 116 1Dh — Unimplemented — — 1Eh ADRESH(2,3) Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 80, 116 1Fh ADCON0(2) ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 78, 116 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: PIC16F616/16HV616 only. 3: Read-only register. |
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